Logic ultra-large-scaled-integrated (ULSI) circuits with embedded DRAM are demanded as high performance devices in order to reduce power consumption and to increase packing density. Self-aligned silicide (salicide) process is one of the most promising technology for deep-submicron logic ULSIs. This is due to the fact that the slicided devices have a lower contact resistance than the non-salicided devices, as reference to IEDM Tech. Dig. p.451, 1996, entitled "A Thermally Stable Ti-W Salicide for Deep-Submicron Logic with Embedded DRAM".
Thus, the salicided device have a faster operation speed than the non-salicided devices. However, the devices with a self-aligned silicided contact shows a worse electrostatic shielding discharge (ESD) performance than the non-salicided devices. As is described as below descriptions in detail, using salicide process have great influence with the performance of devices.
The relation between self-aligned silicide process and the ESD capability have been reported in the article of Amerasekera et al, entitled "Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN behavior, with the ESD/EOS performance of a 0.25 .mu.m CMOS Process", published in IEDM Tech. Dig., p. 893 on 1996. It is noted that the current gain of a self-biased lateral NPN transistor is related to the salicide thickness in a 0.25 .mu.m CMOS process, the relationship between the current gain and the ESD performance was examined in this article. The current gain was strongly influenced by the effective drain/source diffusion depth below the salicide, which was determined by the implant energy and the amount of the active diffusion consumed in silicidation. The devices, with lower current gain, having lower ESD capability are made sure by the authors. The current gain was affected by the NMOS drain junction property so that the ESD performance could be enhanced by either increasing the drain/source implant energy or reducing the salicide thickness. Neither the increase of the implant energy nor the decrease of salicide thickness will significantly change the NMOS characteristic.
A method to fabricate an electrostatic discharge protection circuit is disclosed in U.S. Pat. No. 5,672,527 which was filed on Mar. 8, 1996. The inventors of the patent proposed a method with a photomask instead of several masks as in a conventional process during the salicide process of ESD circuits. However, a complicating etching process was used for accomplishing the salicide process, the devices could be degraded from the etching process. Many stages are used to simultaneously fabricate ESD devices and MOS devices on a substrate in the patent so that the devices have a long processing time and a difficult processing flow.
Another process for fabricating a non-silicided region in an integrated circuit is disclosed in U.S. Pat. No. 5,589,423 of Whit et al for "PROCESS FOR FABRICATING A NON-SILICIDED REGION IN AN INTEGRATED CIRCUIT". The inventive process provided a substrate having a silicide blocking layer overlaying a portion of the substrate surface. After that a silicide layer is formed on a substrate, a mask is formed to overlie a first portion of the silicide blocking layer. A selectively etching process is used to remove the silicide blocking layer on a second portion of that. The first portion of the silicide layer is protected from attacking by chemical etchants using the mask as a protective layer during the etching process. Following the etching process, the mask is stripped and a non-silicided region in an integrated circuit is formed on a substrate.
A non-silicided ESD protective device could be fabricated on a substrate according to the method of U.S. Pat. No. 5,589,423. In the patent, peripheral circuits and ESD protective circuits are simultaneously defined on a semiconductor substrate and a silicide layer is formed on entire regions. Afterwards, a selectively etching process is used to remove the silicide layer on the ESD protective circuits, non-silicided ESD protective circuits are formed on the substrate. Nevertheless, the method according to the patent is used with a complicated etching process and an extra lithography process, and it could length the processing time of integrated circuits.
As stated above, a salicide process for MOS devices without complicated etching process is needed and the ESD performance of the circuits of the MOS devices is not affected by the salicide process.